Memories in computers are arranged in a hierarchical manner because of trade-offs that must be made between speed, storage density, and cost. The fastest, highest cost memory, static random access memory (SRAM), is located as close as possible to the CPU, usually on the same chip. SRAM is limited in storage capacity because of its high cost. Main memory normally consists of dynamic random access memory (DRAM), which, due to its simpler cell layout can be made much denser. It is slower than SRAM because its contents need to be constantly refreshed and also because it is located further from the CPU on separate chips.
A well-known empirical observation is that, on the average, a small portion of the memory is used a large portion of the time. In other words, some of the data are used many times by the CPU while the rest is used only infrequently. Another empirical principle in memory design is locality. It is more likely that a particular datum will be needed soon if it or nearby data was fetched recently. This is why cache memory is useful for speeding up computer systems. A small section of fast but expensive SRAM is used to store data that were more recently read from or written to slower but larger DRAM. The next time this datum is needed, it can be fetched from fast SRAM rather than slow DRAM. On the average this technique can increase system speed dramatically.
This same cache memory principle is also found in the next stage in the memory hierarchy: between DRAM and mass storage devices consisting of magnetic and optical disks. Optical disks are very useful for storage of very large databases (tens of gigabits or more using replaceable disks) and have many important government and commercial applications. Their performance is limited by slow access times (20 to 200 ms) and moderate I/O bandwidths (20 Mbits/s per disk). DRAM caches are currently used to partially offset these limitations in a similar fashion as SRAM caches do for DRAM main memory. However, although DRAM densities are constantly increasing, access times and I/O bandwidths have increased much more slowly due to the nature of DRAM architecture and the trade-offs that must be made when density is increased.
Hence, what is needed is a high capacity memory that would have faster access times and larger bandwidths than realized in traditional memory technologies. This new memory architecture must be adaptable to present technology and meet the requirements of commercial and government applications. The present invention addresses these needs.